Generation and measurement of timing delays by digital phase error compensation

ABSTRACT

A circuit and method for generating a delayed event following a trigger pulse occurring at a random time between clock pulses is disclosed. The circuit includes a clock circuit, a voltage converter, an analog-to-digital converter circuit, a memory storage circuit, and a summing circuit. The method includes representing the time between the triggering pulse and a subsequent clock pulse as a voltage, converting the voltage to a stored digital value, and defining a desired delay time by adding a first time determined by counting a predetermined number of clock cycles to a second time determined by converting the stored digital value first to an analog value and then to a time value.

This application is a divisional of U.S. patent application Ser. No.10/744,834 filed Dec. 23, 2003, which claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application Ser. No. 60/455572, filed on Mar.17, 2003, the disclosure of both which are hereby incorporated byreference herein.

FIELD OF THE INVENTION

This invention relates generally to apparatus and methods for thegeneration of events following a trigger pulse. It is disclosed in thecontext of an electronic circuit and method for the generation of eventsfollowing a trigger pulse when the trigger pulse occurs at anindeterminate time between clock pulses. However, it is believed to beuseful in other applications as well.

BACKGROUND OF THE INVENTION

The generation of events following an input trigger pulse is a commonrequirement in electrical applications. Generally, a timing delaygenerator receives a trigger signal and counts pulses of an internallygenerated master clock to generate a known delay. When the triggersignal is received at a random time between the master clock pulses,there is inherent timing uncertainty. This timing uncertainty, commonlycalled jitter, is caused from the triggering event not being related inphase to the master clock. In particular, the timing uncertainty relatesto the temporal difference between the trigger signal and the masterclock pulse. Therefore, the timing uncertainty relates to the period ofthe master clock. As the frequency, or speed, of the master clock isincreased, and its period proportionally reduced, the maximum timinguncertainty is reduced. However, increasing the speed of the masterclock typically comes at the expense of increased circuit complexity andcost. Additionally, there are practical limits to the speed of a masterclock. For example, in order to decrease the peak timing uncertainty tothe picosecond order of magnitude, a master clock operating at oneterahertz would be required. However, one terahertz clocks are notpractical with currently available technology. Accordingly, there is aneed for methods and apparatus for the generation of precision delaysfollowing trigger pulses which occur at random times between clockpulses.

DISCLOSURE OF THE INVENTION

According to an aspect of the invention, apparatus for generating adelayed event comprises a clock for producing regular clock pulses, avoltage converter for producing a voltage that is directly proportionalto the difference between a triggering pulse and a clock pulse, ananalog-to-digital converter for converting a voltage produced by thevoltage converter to a digital value, and a summing circuit coupled tothe analog-to-digital converter for producing a signal related to thesum of (i) a first time related to a predetermined number of clockpulses and (ii) a second time related to the digital value.

Illustratively according to this aspect of the invention, the voltageconverter for producing a voltage that is directly proportional to thedifference between a triggering pulse and a subsequent clock pulsecomprises a voltage converter for producing a voltage that is directlyproportional to the difference between a triggering pulse and asubsequent clock pulse.

Illustratively according to this aspect of the invention, the summingcircuit coupled to the analog-to-digital converter for producing asignal related to the sum of (i) a first time related to a predeterminednumber of clock pulses and (ii) a second time related to the storabledigital value comprises a summing circuit coupled to theanalog-to-digital converter for producing a signal related to the sum of(i) a first time that is identifiable by counting a predetermined numberof clock pulses and (ii) a second time related to the digital value.

Illustratively according to this aspect of the invention, the summingcircuit coupled to the analog-to-digital converter for producing asignal related to the sum of (i) a first time related to a predeterminednumber of clock pulses and (ii) a second time related to the digitalvalue comprises a summing circuit coupled to the analog-to-digitalconverter for producing a signal related to the sum of (i) a first timerelated to a predetermined number of clock pulses and (ii) a second timethat is identifiable by converting the digital value to an analog valuefollowed by converting the analog value to a time value

Illustratively according to this aspect of the invention, the summingcircuit coupled to the analog-to-digital converter for producing asignal related to the sum of (i) a first time related to a predeterminednumber of clock pulses and (ii) a second time related to the digitalvalue comprises a summing circuit coupled to the analog-to-digitalconverter for producing a signal related to the sum of (i) a first timerelated to a predetermined number of clock pulses and (ii) a second timerelated to the phase error between a leading edge of a clock pulse andthe triggering pulse.

Further illustratively according to this aspect of the invention, theapparatus includes a memory circuit coupled to the analog-to-digitalconverter and the summing circuit, the memory circuit having a memoryregister capable of storing the digital value.

Illustratively according to this aspect of the invention, the memorycircuit comprises a field-programmable gate array.

Further illustratively according to this aspect of the invention, theapparatus includes a digital-to-analog converter for representing thedigital value as an analog voltage, the digital-to-analog convertercoupled to the memory circuit and the summing circuit.

Further illustratively according to this aspect of the invention, theapparatus includes a time converter coupled to the digital-to-analogconverter for representing the analog voltage as a time value.

Illustratively according to this aspect of the invention, the timeconverter comprises a voltage ramp generator.

Illustratively according to this aspect of the invention, the voltageconverter comprises a voltage ramp generator.

Illustratively according to this aspect of the invention, the voltageconverter further comprises a sample-and-hold circuit, a voltagecomparator, and a sampling amplifier.

Illustratively according to this aspect of the invention, the voltageconverter further comprises a control circuit for controlling thequiescent current of the voltage ramp generator.

Illustratively according to this aspect of the invention, the summingcircuit comprises a plurality of delay generator devices.

Illustratively according to this aspect of the invention, the summingcircuit comprises a voltage ramp generator and a comparator, thecomparator having a first input coupled to a reference voltage sourceand a second input coupled to an output of the voltage ramp generator.

Further illustratively according to this aspect of the invention, theapparatus comprises a field programmable gate array for identifying thefirst and the second times.

Further illustratively according to this aspect of the invention, theapparatus comprises a synchronization circuit coupled to the fieldprogrammable gate array for improving the synchronization of the outputsof the field programmable gate array.

Further illustratively according to this aspect of the invention, theapparatus comprises a logic converter circuit for converting a signalfrom a first logic family to a second logic family.

According to an aspect of the invention, a method for generating delayedevents comprises representing the time between a triggering pulse and asubsequent clock pulse as a voltage, converting the voltage to a digitalvalue, and defining a desired delay time following the triggering pulseby (i) identifying a first time and (ii) adding to the first time asecond time determined by converting the digital value to an analogvalue and then converting the analog value to a time value.

Illustratively according to this aspect of the invention, identifying afirst time comprises identifying a time determined by counting apredetermined number of clock cycles.

Illustratively according to this aspect of the invention, identifying afirst time comprises retrieving a stored digital time value, the storeddigital time value representing a predetermined number of clock cycles.

Illustratively according to this aspect of the invention, representingthe time between a triggering pulse and a subsequent clock pulse as avoltage comprises initiating a ramp voltage for the duration of the timebetween the triggering pulse and the subsequent clock pulse.

Illustratively according to this aspect of the invention, converting thevoltage to a stored digital value comprises (i) converting the voltageto a digital value and (ii) storing the digital value in a memorydevice.

Illustratively according to this aspect of the invention, converting thestored digital value first to an analog value and then to a time valuecomprises initiating a ramp voltage for a duration until the rampvoltage is substantially equal to the analog value.

Illustratively according to this aspect of the invention, initiating aramp voltage for a duration until the ramp voltage is substantiallyequal to the analog value comprises holding the ramp voltage at avoltage substantially equal to the analog value.

Illustratively according to this aspect of the invention, holding theramp voltage at a voltage substantially equal to the analog valuecomprises controlling the quiescent current of a ramp generator.

Illustratively according to this aspect of the invention, controllingthe quiescent current of a ramp generator comprises reducing thequiescent current towards zero amps.

Further illustratively according to this aspect of the invention, themethod comprises defining a desired-pulse width by (i) identifying athird time and (ii) adding to the third time a fourth time determined byconverting the stored digital value to an analog value and thenconverting the analog value to a time value.

Illustratively according to this aspect of the invention, identifying athird time comprises identifying a time determined by counting apredetermined number of clock cycles.

Illustratively according to this aspect of the invention, identifying athird time comprises retrieving a stored digital time value, the storeddigital time value representing a predetermined number of clock cycles.

Further illustratively according to this aspect of the invention, themethod comprises producing an output trigger event a duration after thetrigger pulse, the duration being substantially equal to the desireddelay time, the output trigger event having a duration substantiallyequal to the desired pulse width.

Further illustratively according to this aspect of the invention, themethod comprises converting the stored digital value to a leading edgevalue.

Illustratively according to this aspect of the invention, converting thestored digital value to a leading edge value comprises converting thestored digital value to a first time value, calculating a difference ofa period of a master clock and the first time value, and converting thedifference to a digital value.

According to an aspect of the invention, apparatus for generating adelayed event comprises first means for producing regular clock pulses,second means for producing a voltage that is directly proportional tothe difference between a triggering pulse and a clock pulse, third meansfor converting a voltage produced by the second means to a digitalvalue, and fourth means for producing a signal related to the sum of (i)a first time related to a predetermined number of clock pulses and (ii)a second time related to the digital value, the fourth means coupled tothe third means.

Illustratively according to this aspect of the invention, the secondmeans comprises second means for producing a voltage that is directlyproportional to the difference between a triggering pulse and asubsequent clock pulse.

Illustratively according to this aspect of the invention, the fourthmeans for producing a signal related to the sum of (i) a first timerelated to a predetermined number of clock pulses and (ii) a second timerelated to the digital value comprises fourth means for producing asignal related to the sum of (i) a first time that is identifiable bycounting a predetermined number of clock pulses and (ii) a second timerelated to the digital value.

Illustratively according to this aspect of the invention, the fourthmeans for producing a signal related to the sum of (i) a first timerelated to a predetermined number of clock pulses and (ii) a second timerelated to the storable digital value comprises fourth means forproducing a signal related to the sum of (i) a first time related to apredetermined number of clock pulses and (ii) a second time that isidentifiable by converting the digital value to an analog value and thenconverting the analog value to a time value.

Illustratively according to this aspect of the invention, the fourthmeans for producing a signal related to the sum of (i) a first timerelated to a predetermined number of clock pulses and (ii) a second timerelated to the storable digital value comprises fourth means forproducing a signal related to the sum of (i) a first time related to apredetermined number of clock pulses and (ii) a second time related tothe phase error between a leading edge of a clock pulse and thetriggering pulse.

Further illustratively according to this aspect of the invention, theapparatus includes fifth means for storing the digital value, the fifthmeans including a memory register, the fifth means coupled to the thirdmeans and the fourth means.

Illustratively according to this aspect of the invention, the fifthmeans comprises a field-programmable gate array.

Further illustratively according to this aspect of the invention, theapparatus includes sixth means for representing the digital value as ananalog voltage, the sixth means coupled to the fourth means and thefifth means.

Further illustratively according to this aspect of the invention, theapparatus includes seventh means for representing the analog voltage asa time value, the seventh means coupled to the sixth means.

Illustratively according to this aspect of the invention, the seventhmeans comprises a voltage ramp generator.

Illustratively according to this aspect of the invention, the secondmeans comprises a voltage ramp generator.

Illustratively according to this aspect of the invention, the secondmeans further comprises a sample-and-hold circuit, a voltage comparator,and a sampling amplifier.

Illustratively according to this aspect of the invention, the secondmeans further comprises a control circuit for controlling the quiescentcurrent of the voltage ramp generator.

Illustratively according to this aspect of the invention, the fourthmeans comprises a plurality of delay generator devices.

Illustratively according to this aspect of the invention, the fourthmeans comprises a voltage ramp generator and a comparator, thecomparator having a first input coupled to a reference voltage sourceand a second input coupled to an output of the voltage ramp generator.

Further illustratively according to this aspect of the invention, theapparatus comprises a field programmable gate array for identifying thefirst and the second times.

Further illustratively according to this aspect of the invention, theapparatus comprises a synchronization circuit coupled to the fieldprogrammable gate array for improving the synchronization of the outputsof the field programmable gate array.

Further illustratively according to this aspect of the invention, theapparatus comprises fifth means for converting a signal from a firstlogic family to a second logic family.

According to an aspect of the invention, a method for measuring a timebetween two trigger events comprises initiating a first ramp voltage forthe duration of a time between a first trigger event and a subsequentclock pulse, initiating a time counter contemporaneously with the end ofthe first ramp voltage, initiating a second ramp voltage for theduration of a time between a second trigger event and a subsequent clockpulse, terminating the time counter contemporaneously with the end ofthe second ramp voltage, and calculating the delay between the firsttrigger event and the second trigger event.

Further illustratively according to this aspect of the invention, themethod further comprises converting a peak voltage of the first rampvoltage to a first time value and converting a peak voltage of thesecond ramp voltage to a second time value.

Illustratively according to this aspect of the invention, calculatingthe delay between the first trigger event and the second trigger eventcomprises converting a peak voltage of the first ramp voltage to a firsttime value, converting a peak voltage of the second ramp voltage to asecond time value, summing the first time value with the time counter,and subtracting the second time value from the time counter.

According to an aspect of the invention, a method for self-calibrating adelay measurement and generation circuit comprises initiating a firstvoltage ramp for about one clock cycle, storing a first peak voltage ofthe first voltage ramp, initiating a second voltage ramp for about twoclock cycles, storing a second peak voltage of the second voltage ramp,calculating the slope and intercept of a voltage-to-time line includingthe first and second peak voltages.

Illustratively according to this aspect of the invention, storing afirst peak voltage of the first voltage ramp comprises sampling andholding the voltage ramp after about one clock cycle.

Illustratively according to this aspect of the invention, storing asecond peak voltage of the second voltage ramp comprises sampling andholding the voltage ramp after about one clock cycle.

Illustratively according to this aspect of the invention, storing afirst peak voltage of the first voltage ramp comprises converting thefirst peak voltage to a first digital value and subsequently storing thefirst digital value in a memory location.

Illustratively according to this aspect of the invention, storing asecond peak voltage of the second voltage ramp comprises converting thesecond peak voltage to a second digital value and subsequently storingthe second digital value in a memory location.

Further illustratively according to this aspect of the invention, themethod further comprises storing the slope and intercept of thevoltage-to-time line in a memory location.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may best be understood by referring to the followingdetailed description and accompanying drawings which illustrate theinvention. In the drawings:

FIG. 1 illustrates a greatly simplified block diagram of a circuitconstructed according to the disclosure;

FIG. 2. illustrates a block diagram of one embodiment of a circuitconstructed according to the disclosure;

FIG. 3 illustrates a master clock circuit of the circuit illustrated inFIG. 2;

FIG. 4 illustrates an edge detection circuit of the circuit illustratedin FIG. 2;

FIG. 5 illustrates a resynchronization and jitter pulse constructioncircuit of the circuit illustrated in FIG. 2;

FIGS. 6 and 7 illustrate a time-to-voltage converter andanalog-to-digital converter circuit of the circuit illustrated in FIG.2;

FIG. 8 illustrates a memory storage and delay calculation circuit of thecircuit illustrated in FIG. 2;

FIG. 9 illustrates an output synchronization and converter circuit ofthe circuit illustrated in FIG. 2;

FIGS. 10-12 illustrate a delay output circuit of the circuit illustratedin FIG. 2;

FIG. 13 is a process flow diagram of a memory storage and delaycalculation program for use with the circuit illustrated in FIG. 2;

FIG. 14 illustrates a timing diagram of the process illustrated in FIG.13;

FIG. 15 illustrates a process flow diagram of a self-calibration methodfor use with the circuit illustrated in FIG. 2;

FIG. 16 illustrates a timing diagram of the process illustrated in FIG.15;

FIG. 17 illustrates a process flow diagram of a delay time measurementmethod of the circuit illustrated in FIG. 2; and

FIG. 18 illustrates a timing diagram of the process illustrated in FIG.17.

DETAILED DESCRIPTIONS OF ILLUSTRATIVE EMBODIMENTS

While the disclosure is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and will herein be described in detail. Itshould be understood, however, that there is no intent to limit thedisclosure to the particular forms disclosed, but on the contrary, thedisclosure is to cover all modifications, equivalents, and alternativesfalling within the spirit and scope of the disclosure as defined by theappended claims.

In the detailed descriptions that follow, several integrated circuitsand other components are identified, with particular circuit types andsources. In many cases, terminal names and pin numbers for thesespecifically identified circuit types and sources are noted. This shouldnot be interpreted to mean that the identified circuits are the onlycircuits available from the same, or any other, sources that willperform the described functions. Other circuits are typically availablefrom the same, and other, sources which will perform the describedfunctions. The terminal names and pin numbers of such other circuits mayor may not be the same as those indicated for the specific circuitsidentified in this description of illustrative embodiments.

Referring now to FIG. 1, an illustrative circuit 10 generates delayedoutput events (e.g., output trigger pulses after a delay time) after atrigger pulse which occurs at a random time relative to an internalpulse from a master clock. Circuit 10 includes a master clock circuit12, a trigger detection circuit 14, a resynchronization and jitter pulseconstruction circuit 16, a time-to-voltage converter (hereinaftersometimes TVC) and analog-to-digital converter (hereinafter sometimesADC) circuit 18, a memory storage and delay calculation circuit 20, anda delay output circuit 22. The master clock circuit 12 produces regularclock pulses which are received by circuits 16 and 20. The triggerdetection circuit 14 detects the occurrence of a trigger event or pulseand produces a trigger signal corresponding to the trigger event. Theresynchronization and jitter pulse construction circuit 16 receives thetrigger signal and constructs a trigger jitter pulse corresponding tothe trigger pulse and a subsequent clock edge. The TVC and ADC circuit18 converts the trigger jitter pulse to a digital value and the memorystorage and delay calculation circuit 20 stores the digital value. Thecircuit 20 also calculates the final delay time which, in someembodiments, may include summing the digital value with a predeterminedarbitrary delay time. Additionally, in some embodiments, the circuit 20calculates an arbitrary output pulse width. The delay output circuit 22communicates with circuit 20 to produce an output pulse after theexpiration of the appropriate delay time having a pulse widthsubstantially equal to the arbitrary output pulse width.

Only one of many possible embodiments of the present disclosure is shownillustratively in FIG. 1. In other embodiments, the functionality of thecircuits 12, 14, 16, 18, 20, and 22 may be otherwise divided. Forexample, the functionality of circuit 18 can be provided by separatetime-to-voltage converter and analog-to-digital converter circuits. Inother embodiments, the functionality of two or more of the circuits 12,14, 16, 18, 20, and 22 may be combined into a single circuit. Forexample, the functions of circuits 12 and 14 can be combined into asingle trigger detection, resynchronization, and jitter pulseconstruction circuit. Further, although only one illustrative delayoutput circuit 22 is shown and described herein, it is contemplated thatalternative embodiments of circuit 10 may include any number of delayoutput circuits 22 to thereby increase the number of output channels ofthe circuit 10. Additionally, the functionality of the complete circuit10, or a portion thereof, may be implemented in a single or multipleintegrated chip(s). The circuit illustrated in FIG. 1 may also beincluded as a component of a larger circuit.

The circuit 10 may be implemented using any one or more of a number ofcontrol logics. The illustrative circuit 10 described hereinafter use acombination of positive emitter coupled logic (hereinafter sometimesPECL) having a logic high level value of approximately 4.0 volts and alogic low-level value of approximately 3.25 volts, negative emittercoupled logic (hereinafter sometimes NECL) having a logic high levelvalue of approximately −0.8 volts and a logic low level value ofapproximately −1.75 volts, transistor-transistor logic (hereinaftersometimes TTL) having a logic high level value of approximately 5 voltsand a logic low level value of approximately 0 volts, and complimentarymetal-oxide semiconductor (hereinafter sometimes CMOS) logic. However,in alternative embodiments, circuit 10 may be implemented using anysingle logic family including other logic families such as, for example,low voltage differential signal (hereinafter sometimes LVDS) logic, orany combination of logic families as desired in the particularimplementation.

One illustrative embodiment of circuit 10 is shown in FIG. 2. A circuit30 for generating events after a pulse which occurs at a random timerelative to an internal pulse from a master clock includes a masterclock circuit 32, a trigger detection circuit 34, a resynchronizationand jitter pulse construction circuit 36, a time-to-voltage converter(hereinafter sometimes TVC) and analog-to-digital converter (hereinaftersometimes ADC) circuit 38, a memory storage and delay calculationcircuit 40, an output synchronization and converter circuit 41, and adelay output circuit 42.

Referring now to FIGS. 2 and 3, the master clock circuit 32 iselectrically coupled to circuits 36, 40, and 41. The master clockcircuit 32 generates clock pulses which are received by circuits 36, 40,and 41. In the illustrative embodiment, the master clock 32 producesregular square wave clock pulses. However, other types of regular clockpulses may be generated. Clock circuits for the generation of regularclock pulses are widely known to those skilled in the art. In theillustrative embodiment of FIG. 3, PECL regular clock pulses areproduced by a clock generator 50, illustratively an On Semiconductortype NBC 12430/LQFP 3.3V/5V Programmable PLL Synthesized ClockGenerator. A number of control signals, TTL_CLK_SCLK, TTL_CLK_SD,TTL_CLK_SLD, are used to program the functions (e.g., clock frequency)of the clock generator 50. In the illustrative circuit 30, the CLK_SCLK,TTL_CLK_SD, TTL_CLK_SLD signal lines are coupled to the memory storageand delay calculation circuit 40 which is configured to produce theappropriate control signals. However, in other embodiments, the controlsignals may be produced via a separate control circuit or the like. Thefunctions of the clock generator 50 may be monitored by monitoring aclock test signal, TTL_CLKTEST. For example, in the illustrativeembodiment of circuit 30 the TTL_CLK_TEST signal line is coupled to thecircuit 40 which is configured to perform the monitoring functions.Additionally, the output of the clock generator 30 is controllable by aclock enable signal, TTL_CLOCK_EN, received on an output enableterminal, OE, of the generator 50. In the illustrative embodiment ofFIG. 3, the TTL_CLOCK_EN signal line is coupled to the circuit 30 whichis configured to produce the appropriate clock enable signal.

The frequency of the clock generator 50 is determined, in part, by acrystal oscillator 52. The oscillator 52 is a temperature or “oven”compensated crystal oscillator, but other types of oscillators may beused. Illustratively, the oscillator 52 is an ILSI America type VCTCXO1302 Series DIP Clipped Sinewave oscillator. An FOUT terminal of theoscillator 52 is coupled to an FREF_EXT terminal of the clock generator50. An Fadj terminal of the oscillator 32 is coupled to an FADJ signalline. The FADJ signal is used to control the operation (e.g., theoscillating frequency) of the oscillator 52.

The clock generator 50 is also coupled to a clock distribution device54. In the illustrated embodiment of FIG. 3, the clock distributiondevice 54 is an ON Semiconductor type MC 100EL15 5V ECL 1:4 ClockDistribution Chip. The input terminals, #CLK and CLK, of thedistribution device 54 are coupled to the output terminals, #FOUT andFOUT, respectively, of the clock generator 50. The distribution device54 distributes the clock signal across four outputs (or more outputs inembodiments using a distribution device having additional distributionoutputs). Three sets of outputs of the device 54, Q0 and #Q0, Q1 and#Q1, and Q2 and #Q2, are coupled to the 100 MHZ_PECL1 signal lines, 100MHZ_PECL2 signal lines, and the 100 MHZ_PECL3 signal lines,respectively. The fourth set of outputs, Q3 and #Q3, are coupled to atranslator 56, illustratively an ON Semiconductor type MC100ELT21 5VDifferential PECL to TTL Translator. The translator 56 converts the PECLclock pulses produced on the output terminals Q3 and #Q3 of the device54 to TTL clock pulses for use with devices requiring TTL logic. Theoutput, Q, of the translator 56 is coupled to the 100 MHZ_TTL signalline. The collection of clock signal lines, 100 MHZ_TTL, 100 MHZ_PECL1,#100 MHZ_PECL1, 100 MHZ_PECL2, #100 MHZ_PECL2, 100 MHZ_PECL3, and #100MHZ_PECL3, form a clock bus, CLK_BUS signal line, which is coupled tothe memory storage and delay calculation circuit 40 as illustrated inFIG. 2.

Although only one exemplary embodiment of a master clock circuit isshown in FIG. 3, other methods and circuits for producing regular clockpulses may be used. For example, 555 timer circuits, capacitordischarging circuits, and other integrated and discrete-component timingcircuits may be used to construct the master clock circuit 32 andproduce regular clock pulse.

Referring now to FIG. 4, the trigger detection circuit 34 detects thepresence of a trigger event received on an input signal line. In theillustrated embodiment of FIG. 4, the trigger event is detected by awindow comparator with two predetermined reference voltages. The windowcomparator is formed from a predetermined maximum voltage reference anda predetermined minimum voltage reference. In some embodiments, thereference voltages may be buffered using, for example, differentialamplifiers. The voltage level of the trigger event must fall within thevoltage window created by these predetermined maximum and minimumvoltage references for the trigger event to be recognized by the circuit34. The illustrative trigger detection circuit 34 includes twocomparators 60, 62. A maximum voltage reference, TW0, signal line iscoupled to the IN+ input terminal of comparator 60. Comparator 60illustratively is a Maxim type MAX9601 dual PECL ultra-high-speedcomparator. The IN− input terminal of comparator 60 is coupled to a port64 carrying the trigger event or pulse. In this configuration,comparator 60 compares the maximum voltage reference signal, TW0,applied to its IN+terminal and the voltage level of any trigger eventapplied to the IN− terminal. If the voltage level of the trigger eventfalls below the maximum voltage reference, the comparator 60 willproduce a PECL low level signal at the #Q output terminal. The minimumvoltage reference, TW1, signal line is coupled to the IN− input terminalof comparator 62. Comparator 62 also illustratively is a Maxim typeMAX9601 comparator. The IN+ input terminal of the comparator 62 iscoupled to the IN− input terminal of comparator 60 and to the port 64carrying the trigger event. In this configuration, comparator 62compares the minimum voltage reference signal, TW1, applied to the IN−terminal and the voltage level of any trigger event applied to the IN+terminal. If the voltage level of the trigger event falls above theminimum voltage reference, the comparator 62 will produce a PECL lowlevel signal at the #Q output terminal. The #Q output terminals of thecomparators 60, 62 are coupled together in a wired-OR configuration to a#WINDOW_OUT_PECL signal line. Accordingly, a logic low window triggersignal is produced on the #WINDOW_OUT_PECL signal line when the triggerevent voltage is within the voltage window determined by the voltagereferences. The voltage reference signals, TW0 and TW1, may be producedby the memory storage and delay calculation circuit 20, a separatecontrol circuit, or tied to a constant voltage reference signal. Thewindow can be adjusted as required by the application by adjusting thevoltage reference signals, TW0 and TW1.

The resynchronization and jitter pulse construction circuit 36 preservesthe leading edge of the trigger event signal and synchronizes thetrailing edge of the trigger signal with a subsequent clock transition.In the illustrated embodiment, the trigger signal is constructed andsynchronized by the cooperation of a plurality of flip-flops. Referringparticularly to FIG. 5, the illustrative resynchronization and jitterpulse construction circuit 36 includes a D flip-flop 70. Illustratively,the D flip-flop 70 is an ON Semiconductor type MC100EL31 5V ECL Dflip-flop with Set and Reset. Circuit 36 further includes a shiftregister 71 comprising two D flip-flops 72, 74, also illustrativelyMC100EL31 flip-flops, and an exclusive-OR(hereinafter sometimes XOR)gate 76, illustratively an ON Semiconductor type MC100EL07 5V ECL2-input XOR/XNOR gate.

The #WINDOW_OUT_PECL signal line is coupled to a first input terminal ofthe XOR gate 76. A TRIG_POLARITY_PECL signal line is coupled to a secondinput terminal of the XOR gate 76. The trigger polarity signal controlsthe polarity of the window trigger signal and may be used to change thepolarity by causing the XOR gate 58 to function as an inverter. Thisfunctionality allows subsequent circuit triggering on either the risingor the falling edge of the #WINDOW_OUT_PECL signal, and thereby, thetrigger event signal. The TRIG_POLARITY_PECL signal may be a presetlogic entity configured during trigger setup or may be produced by acontrol circuit. Illustratively, as shown in FIG. 2, theTRIG_POLARITY_PECL signal line is coupled to the output synchronizationand converter circuit 41. The trigger polarity signal is produced by thememory storage and delay calculation circuit 40 as a TTL signal (i.e.,TTL_TRIG_POLAR) and converted from the TTL signal to a PECL signal(i.e., TRIG_POLARITY_PECL) by the circuit 41 as described below inregard to FIG. 9. During normal operation, the TRIG_POLARITY_PECL signalis held at a logic low thereby inverting the #WINDOW_OUT_PECL signal.

The Q output terminal of the XOR gate 76 is coupled to a CLK terminal ofthe flip-flop 70. The flip-flop 70 may be configured via a number ofcontrol signals, ARM_PECL and TRIG_INHIB_PECL. The ARM_PECL signal lineis coupled to the set terminal, S, of the flip-flop 70 and the ARM_PECLsignal is used to preset the output of the flip-flop 70. TheTRIG_INHIB_PECL signal line is coupled to the data terminal, D, of theflip-flop 70 and the TRIG_INHIB_PECL signal is used to configure thelogic level of the output of the flip-flop 70 after a triggering event(i.e., a rising edge of the inverted #WINDOW_OUT_PECL signal). Theflip-flop control signals, ARM_PECL and TRIG_INHIB_PECL, may also bepreset logic entities configured during setup or may be produced by acontrol circuit. In the illustrated embodiment, the arm and triggerinhibit control signals are produced by the circuit 40 as TTL signals(i.e., TTL_ARM and TTL_TRIG_INHIB, respectively) and converted from theTTL signal to a PECL signal (i.e., ARM_PECL and TRIG_INHIB_PECL,respectively) by the circuit 41. During normal operation, the flip-flop70 is preset to a logic high by the ARM_PECL and the TRIG_INHIB_PECL isheld to a logic low to provide a logic low output of the flip-flop 70after the triggering of the flip-flop 70.

The rising edge of the inverted #WINDOW_OUT_PECL signal triggers theflip-flop 70, producing a falling edge on the Q output terminal offlip-flop 70. The Q output terminal of flip-flop 70 is coupled to afirst input terminal of an OR gate 78. The OR gate 78 illustratively isan ON Semiconductor type MC100EL01 5V ECL 4-input OR/NOR gate.

The 100 MHZ_PECL1 master clock signal line is coupled to the CLKterminals of the flip-flops 72, 74 of the shift register 71. The D inputterminal of the flip-flop 72 is coupled to the #Q output terminal offlip-flop 70. When the flip-flop 70 is triggered, a rising edge or highlogic signal is produced on the #Q terminal of the flip-flop 70. Thishigh logic signal is propagated through the shift register 71. The shiftregister 71 produces a logic high output signal that is substantiallycoincident with a master clock transition. The Q output terminal of theflip-flop 74 of the shift register 71 is coupled to a second inputterminal of OR gate 78. The OR gate 60, therefore, produces a “triggerjitter” output signal which is indicative of the asynchronicity of theinitial trigger pulse or event plus one or more clock cycles asdetermined, in part, by the number of flip flops included in the shiftregister 71. In the illustrated embodiment of FIG. 5, the output signalof the OR gate 78 is indicative of the asynchronicity of the initialtrigger event plus one additional clock cycle. The output signal of theOR gate 78 comprises the asynchronous falling edge output of flip-flop70 and the synchronous rising edge output of shift register 71. The Qand #Q terminal outputs of OR gate 78 are coupled to theTRIG_JITTER_PECL and #TRIG_JITTER_PECL signal lines, respectively.

Referring now to FIGS. 6 and 7, the Time-to-Voltage andAnalog-to-Digital Converter circuit 38 converts the trigger jittersignal to an analog voltage and the analog voltage to a digital value.The TVC and ADC circuit 38 includes a Time-to-Voltage circuit 80illustrated in FIG. 6 and an Analog-to-Digital Converter circuit 82illustrated in FIG. 7. In the illustrated embodiment of FIGS. 6 and 7,the trigger jitter signal is converted to an analog voltage byinitiating a ramp generator for the duration of the resynchronizedtrigger jitter signal. The analog voltage value produced by the rampgenerator is held for a time period suitable for an analog-to-digitalconverter to convert the analog voltage value to a digital value. Thedigitized voltage is thereby substantially proportional to the triggerjitter signal pulse width which is substantially proportional to thephase difference of the trigger event and a subsequent clock pulse. Theillustrative TVC circuit 80 includes a translator 84 and a rampgenerator 86. The illustrative ADC circuit 82 includes ananalog-to-digital converter 88. Translator 72 illustratively is an ONSemiconductor type MC100ELT21 5V Differential PECL to TTL Translator.The Ramp generator 74 illustratively is a Burr-Brown type OPA660BB widebandwidth operational transconductance amplifier and buffer. TheAnalog-to-digital converter 78 illustratively is an Analog Devices typeAD9220 A/D converter.

As shown in FIG. 6, the TRIG_JITTER_PECL and #TRIG_JITTER_PECL signallines are respectively coupled to the D and #D input terminals of thetranslator 84. The translator 84 converts the PECL trigger jitter signalto a TTL output signal having a width corresponding to the width of thetrigger jitter signal. The Q output terminal of the translator 84 iscoupled to the Vin (or Base) input terminal of an operationaltransconductance amplifier 90 of the ramp generator 86, which isconfigured as an integrator. The Collector terminal of the operationaltransconductance amplifier 90 is coupled to the INput terminal of abuffer amplifier 92 of the ramp generator 86. A ramp voltage (i.e., theRAMP_OUT signal) is produced at the OUTput terminal of the generator 86.The final ramp voltage is substantially proportional to the triggerjitter signal pulse width.

The final ramp voltage produced by the ramp generator 86 is held for atime period suitable for the ADC circuit 82 to convert the final rampvoltage to a digital value. In the illustrative embodiment of FIGS. 6and 7, the quiescent current of the operational transconductanceamplifier 90 is controlled (i.e., the quiescent current is reducedtoward zero) so as to cause the generator 86 to maintain the final rampvoltage for a short period of time (i.e., approximately 500nanoseconds). Accordingly, a quiescent current adjust terminal, Iq, ofthe operational transconductance amplifier 90 is used to reduce thequiescent current of the ramp generator 86 to substantially zero amps.To do this, a switch 94, illustratively a Fairchild type MMBTH81 PNPTransistor, is coupled to the Iq terminal of the amplifier 90. Theswitch 94 is controlled by a TTL_HOLD control signal applied to the baseterminal of the switch 94. The quiescent current of the ramp generator74 may be adjusted (e.g., reduced toward zero) by adjusting the TLL_HOLDsignal (i.e., applying a logic low level to the base of the switch 76).The TTL_HOLD signal may be a preset logic entity configured at setup ormay be produced by a control circuit. Illustratively, the TTL_HOLDsignal is produced by the memory storage and delay calculation circuit40, as shown in FIG. 2. However, other methods of maintaining the finalramp voltage for a suitable time period may be used. For example, theoutput of the ramp generator 86 may be coupled to a sample and holdcircuit configured to sample the final ramp voltage and hold the voltagevalue long enough for the ADC circuit 82 to convert the voltage value toa representative digital value.

The RAMP OUT signal produced by the ramp generator 86, is supplied tothe analog-to-digital converter 88 of the ADC circuit 82 on the VINAinput terminal as illustrated in FIG. 6. The ADC 82 converts the rampvoltage to a twelve bit digital value. The digital value is a digitalrepresentation of the pulse width between the asynchronous trigger eventand a subsequent internal clock pulse. The digital value is produced onthe output port, terminals D0-D11, of the ADC 88. It should beappreciated that ADCs having lesser or greater resolution (i.e., outputbits) may be used so as to increase or decrease the resolution of thedigital value according to the requirements of the particularimplementation.

Referring back to FIG. 2, the memory storage and delay calculationcircuit 40 stores the digital value representing the pulse width betweenthe asynchronous trigger event and a subsequent internal clock pulse ina memory circuit and calculates the appropriate delay time intervals.Storing the representation value digitally in memory improves the driftover time of the representation value compared to an analog storagedevice, for example, a capacitor storage circuit. The circuit 40 alsocalculates two distinct time intervals. The first time intervalcalculated by the circuit 40 is the predetermined, arbitraryinitialization delay time of the delayed output event (i.e., the time todelay the beginning of the output trigger pulse). The second timeinterval calculated by the circuit 40 is the predetermined, arbitrarypulse width of the delayed output event (i.e., the pulse width of theoutput trigger pulse). The two time intervals are embodied as digitalrepresentations of time values which are predetermined during setup. Inthe illustrated embodiment of FIG. 2, the two time intervals are storedin the circuit 40. However, the two time intervals may be determined,altered, or otherwise supplied to the circuit 30 during runtimeconditions and may be stored or produced by other sub-circuitselectrically coupled to circuit 40 such as a bank of selectable switchesor the like.

Referring now generally to FIGS. 8-12, the two time intervals are usedin conjunction with the stored digital value representing the pulsewidth between the trigger event and a subsequent master clock pulse, orcalculated digital values based thereon, to produce a delayed outputevent having an initialization delay approximately equal to thearbitrary initialization delay time and a pulse width substantiallyequal to the arbitrary pulse width time. To do so, the arbitraryinitialization delay time is summed with the digital value to produce afinal initialization delay time. After the lapse of this finalinitialization delay time, the delayed output event or pulse isinitialized. The arbitrary pulse width time is also summed with thedigital value to produce a final pulse width time. After the lapse ofthis final pulse width delay time, the delayed output event or pulse isterminated. In the illustrated embodiment, the arbitrary initializationdelay time and the digital value representing the pulse width betweenthe trigger event and a subsequent master clock pulse are summed byconverting the stored digital value to an analog value and further to atime value after the lapse of the arbitrary initialization delay.Subsequently, the delayed output event or pulse is initiated. Similarly,the arbitrary pulse width time and the digital value are summed byconverting the stored digital value to an analog value and further to atime value after the lapse of the arbitrary pulse width timeSubsequently, the delayed output event or pulse is terminated. In otherembodiments, the two time intervals may be summed separately with thedigital value internally within the circuit 40. The delayed output pulsemay then be initialized after the expiration of the final initializationdelay time, as counted or otherwise determined by the circuit 40, andterminated after the expiration of the final pulse width time, ascounted or otherwise determined by the circuit 40. Regardless of thesummation process used, it should be appreciated that the digital valuessummed with the two time intervals may be the stored digital valuerepresenting the pulse width between the trigger event and a subsequentmaster clock pulse or calculated digital values based on the storeddigital value. The two calculated digital values may be the same valueor different values for each separate time interval. Such calculateddigital values may be used in those embodiments where the arbitraryinitialization delay may be a non-multiple of the master clock period(see the discussion of FIG. 11), other extraneous values are accountedfor such as calibration factors, and the like.

In the illustrated embodiment, the digital value representing the pulsewidth between the trigger event and a subsequent master clock pulse isstored in a memory register. The two distinct time intervals arecalculated by a programmable processing circuit as discussed below inregard to FIGS. 8 and 11. The stored digital value, or calculateddigital values based thereon, is converted to an analog value by adigital-to-analog converter and further converted to a timerepresentation value by a voltage-to-time converter as discussed belowin regard to FIGS. 10-12.

Referring now particularly to FIG. 8, illustratively, the functions ofthe memory storage and delay calculation circuit 40 are programmed intoa Field-Programmable Gate Array device 100 (hereinafter sometimes FPGA).However, in other embodiments the functions of the circuit 40 mayprogrammed into other types of integrated circuits or be implementedusing discrete circuits and/or sub-circuits. The FPGA 100 illustrativelyis an Altera type APEX 20K FPGA. The functionality of circuit 40 isembodied as a software program stored in the FPGA 100 and written usingVery High Speed Integrated Circuit Hardware Description Language(hereinafter sometimes VHDL). The FPGA 100 receives the digital valuerepresenting the pulse width between the trigger event and a subsequentmaster clock pulse on the D0-D11 signal lines. The digital value isstored within memory locations or registers in the FPGA 100. The FPGA100 produces the stored digital value, or calculated digital valuesbased on the stored digital value, on output data linesDATA_OUT0-DATA_OUT11. The digital value used in summation with thearbitrary initialization delay time and the digital value used insummation with the arbitrary pulse width time are multiplexed on theDATA_OUT data lines using the WRT1 and WRT2 control signals.Accordingly, the FPGA 100 can produce similar or different storeddigital values, or calculated digital values based thereon, forsummation with each of the arbitrary time intervals. The FPGA 100determines the two time intervals via retrieving digital representationsof the time intervals from memory locations or registers, or inalternative embodiments, may receive the time interval values on inputsignal lines. After the lapse of the arbitrary initialization delaytime, as determined by the FPGA 100 by counting the appropriate masterclock cycles, the FPGA 100 produces a trigger signal or pulse on theTTL_START_1 signal line. Similarly, after the lapse of the arbitrarypulse width time, as determined by the FPGA 100 by counting theappropriate master clock cycles, the FPGA produces a trigger signal orpulse on the TTL_STOP_1 signal line. Although the illustrativeembodiment illustrates only one output channel, the FPGA 100 can beconfigured to accommodate multiple output channels having alternativetime intervals produced on other TTL_START and TTL_STOP signal lines.The FPGA 100 also produces a number of control signals, as illustratedin FIGS. 2 and 8, for controlling various circuits of circuit 10.

A process flow diagram of a program 160 for use with the FPGA 100 isillustrated in FIG. 13. Illustratively, the program 160 is programmedinto the FPGA 100 using VHDL. See the discussion of FIG. 8. The program160 begins with a process step 162 in which portions of the FPGA 100 areinitialized. For example, the desired arbitrary initialization delaytime and the arbitrary pulse width time values may be retrieved frommemory locations of the FPGA 100, or alternatively, from associatedmemory devices or input ports of the FPGA 100. The two time values areused to calculate the final initialization delay time and the pulsewidth of the delayed output event. In process step 164, the arbitraryinitialization delay time value is divided by the period of the masterclock. The quotient of the operation of process step 164 is loaded intoa synchronous timer 1 (e.g., an internal data accumulator, register,memory location, or the like) in process step 166. In the illustrativeembodiment, two clock cycles are subtracted from the quotient of theoperation of process step 164 to account for the additional clock cycleinherent in the voltage ramp and the leading edge calculation of thetrigger event as discussed below in regard to process step 184. Also inprocess step 166, the remainder of the operation of process step 164 isloaded into an asynchronous timer 1 (e.g., an internal data accumulator,register, memory location, or the like), the arbitrary pulse width delaytime value is stored in a synchronous timer 2 (e.g., an internal dataaccumulator, register, memory location, or the like), and the triggercircuit is armed. An exemplary arbitrary initialization delay time 200and an exemplary arbitrary pulse width time 202 are illustrated in FIG.14.

In process step 168, program 160 determines if a trigger event 206 hasoccurred. The FPGA 100 may determine that a trigger event has occurredby receiving a trigger pulse received on the TTL_TRIG_OUT signal line asillustrated in FIG. 2. If no trigger event 206 has been received, theprogram 160 continues to monitor for the trigger event 206. Once atrigger event 206 has been received, a synchronous counter is initiatedin process step 170. The synchronous counter begins to count masterclock cycles beginning with the next clock pulse after the trigger eventor pulse as illustratively shown in FIG. 14 as initialization count 210.In addition, a voltage ramp 208 is initiated contemporaneously with thetrigger event 206 (see discussion of FIG. 6). For example, asillustrated in FIG. 14, the ramp 208 is initiated at a time point 212.The time point 212 may or may not be synchronous with the trigger event206 due to inherent delays (e.g., component propagation delays) withincircuit 30. The ramp 208 continues to rise until a convenient leadingedge of the master clock pulse train 204. Illustratively, the ramp 208continues for a time period equal to the phase error between the triggerevent 206 and the leading edge of the subsequent clock cycle of themaster clock pulse train 204 plus one additional clock cycle, i.e., atime point 214 at the rising edge of the second master clock cycle afterthe detection of the trigger event 206. As is the case with time point212, the time point 214 may or may not occur synchronously with therising edge of a clock pulse of the master clock pulse train 204 due toinherent delays within circuit 30. However, the inherent delays withincircuit 30 are accounted for during a self-calibration method 230 whichwill be discussed below in connection with FIGS. 15 and 16. The voltagevalue of the ramp 208 is held at the final ramp value (i.e., the valueat time point 214) for a period of time suitable to convert the analogvoltage value to a digital value which thereby represents the pulsewidth between the trigger event 206 and the second subsequent clockpulse of the master clock pulse train 204 (see discussion of FIG. 6).

In process step 172, the digital value representing the pulse widthbetween the trigger event 206 and the second subsequent master clockpulse is received and read by the FPGA 100 on the DO-D11 data lines. Thedigital value is subsequently stored in memory in process step 174.Illustratively, the digital value is stored in an asynchronous timer 2(e.g., an internal data accumulator, register, memory location, or thelike). The digital value is converted to a time value in process step176. The digital value is converted using the calibration coefficientsas determined by the self-calibration method 230 discussed below inregard to FIGS. 15 and 16. In process step 178, the converted time valueis summed with the time value (i.e., the quotient of process step 164)previously stored in the asynchronous timer 1 (process step 166) and thesum of this addition is stored in the asynchronous timer 1.

In process step 180, the program 160 determines if the time value storedin the asynchronous timer 1 is greater than one master clock cycle. Ifthe time value stored in the asynchronous timer 1 is not greater thanone master clock cycle, the program 160 skips process step 182 andadvances to process step 184 which will be discussed below. If the timevalue stored in the asynchronous timer 1 is greater than one masterclock cycle, in process step 182, one clock cycle is subtracted from theasynchronous time 1 and one clock cycle is added to the synchronoustimer 1. In process step 184, the time values stored in the asynchronoustimer 1 and timer 2 are converted to leading edge voltage values usingthe calibration coefficients as determined by the self-calibrationmethod 230 discussed below in regard to FIGS. 15 and 16. Each of thetime values stored in the asynchronous timer 1 and timer 2 are convertedto leading edge time values by subtracting their current time valuesfrom the period of the master clock. The resultant leading edge timevalues represent the pulse width from the start of the clock cycle inwhich the trigger event occurred to the trigger event. In the case ofthe asynchronous timer 1, the leading edge time value may also includeany asynchronous portion of the arbitrary initialization delay time asdiscussed above in regard to process steps 164 and 166. The leading edgetime values are subsequently converted to voltage values using thecalibration coefficients.

In process step 186, the program 160 determines if the time value storedin the synchronous timer 1 has elapsed. The FPGA 100 determines theelapse of the synchronous timer 1 by comparing the synchronous counter(i.e., the number of elapsed clock cycles) with the synchronous timer 1.If the synchronous timer 1 has not elapsed, the synchronous countercontinues to count clock cycles until the number of counted clock cyclesequals the time value stored in the synchronous timer 1. If thesynchronous timer 1 has elapsed, the synchronous counter is restarted inprocess step 188. The synchronous counter begins counting the masterclock cycles contemporaneously with the end of the first synchronouscounter as illustratively shown in FIG. 14 as pulse width count 220. Inprocess step 190, the voltage value stored in the asynchronous timer 1is written to the output port of the FPGA 100 and appears on the outputsignal lines DATA_OUT[0 . . . 11]. As discussed above in regard to FIG.8, the output data is multiplexed on the DATA_OUT[0 . . . 11] data linesand, consequently, the WRT1 signal is used to identify that the voltagevalue stored in the asynchronous timer 1 is being written to theDATA_OUT[0 . . . 11] data lines. The initialization delay ramp 216 isalso triggered in process step 190 and rises to a target voltage (attime point 218) determined by the voltage value written to the outputport, thereby converting the voltage value to a time value.Illustratively, the initialization delay ramp is triggered via theTTL_START_1 signal (see FIG. 11)

The program 160 determines if the time value stored in the synchronoustimer 2 has elapsed in process step 192. The FPGA 100 determines theelapse of the synchronous timer 2 by comparing the synchronous counter(i.e., the number of elapsed clock cycles) with the synchronous timer 2.If the synchronous timer 2 has not elapsed, the synchronous countercontinues to count clock cycles until the number of counted clock cyclesequals the time value stored in the synchronous timer 2. If thesynchronous timer 1 has elapsed, the voltage value stored in theasynchronous timer 2 is written to the output port of the FPGA 100 inprocess step 194 and appears at the output signal lines DATA_OUT[0 . . .11]. The WRT2 signal is used to identify that the voltage value storedin the asynchronous timer 1 is being written to the DATA_OUT[0 . . . 11]signal lines. The pulse width time ramp 222 is also triggered in processstep 194 and rises to a target voltage (at time point 224) determined bythe voltage value written to the output port, thereby converting thevoltage value to a time value. Illustratively, the initialization delayramp is triggered via the TTL_STOP_1 signal.

An output pulse 226 is produced which includes an initialization edgecorresponding to the time point 218 at which the initialization delayramp reached the target voltage value as determined by the asynchronoustimer 1 and a terminating edge corresponding to the time point 224 atwhich the pulse width time ramp reached the target voltage value asdetermined by the asynchronous timer 2. Therefore, the output pulse 226has an initialization delay substantially equal to the sum of thearbitrary initialization delay and the phase error of the trigger eventand a pulse width substantially equal to the arbitrary pulse width time.In process step 196, the trigger circuit is rearmed and the program 160loops back to process step 168 to monitor for another trigger event.

Referring now to FIG. 9, the output synchronization and convertercircuit 41 synchronizes a number of the outputs of the memory storageand delay calculation circuit 40 (i.e., the FPGA 100) and converts theoutputs of the circuit 41 from TTL outputs to ECL outputs as required bysubsequent circuits. The circuit 41 may not be required in thoseembodiments in which the memory storage and delay calculation circuit 40exhibits minimal jitter between outputs. Additionally, in embodiments inwhich the circuit 30 is implemented using a single logic family or inwhich the logic family of the outputs of circuit 40 match the logicfamily of the circuits receiving said outputs, the outputs of thecircuit 40 need not be converted.

The circuit 41 includes a synchronization circuit 110 and a number ofconverter circuits 112, 116, 118, 120, and 122. The synchronizationcircuit 110 includes two translators 124, 126 and a register 128.Illustratively, the translators 124, 126 are two portions of an ONSemiconductor type MC100ELT22 5V dual TTL to differential PECLtranslator and the register 128 is an ON Semiconductor type MC10EP4513.3V/5V ECL 6-Bit differential register. The input terminal, D0, of thetranslator 124 is coupled to the TTL_START_1 signal line and the inputterminal, D1, of translator 126 is coupled to the TTL_STOP_1 signalline. The translators 124, 126 convert the TTL_START_1 and TTL_STOP_1signals produced by the circuit 40 to PECL signals. The outputs, Q and#Q, of translator 124 are coupled to the D0 and #D0 input terminals ofthe register 128. The outputs, Q and #Q, of translator 126 are coupledto the D1 and #D1 input terminals of the register 128. The clockterminals, CLK and #CLK, of the register 128 are coupled to the 100MHZ_PECL and #100MHZ_PECL master clock signal lines. The Q0 and #Q0output terminals of register 128 are coupled to the TRIG_START_PECL and#TRIG_START_PECL signal lines, respectively, of the register 128.Similarly, the Q1 and #Q1 output terminals of the register 128 arecoupled to the TRIG_STOP_PECL and #TRIG_STOP_PECL signal lines,respectively, of the register 128. The register 128 minimizes any jitterpresent in the outputs of the memory storage and delay calculationcircuit 40 by synchronizing the start and stop signals with the masterclock.

Each of the converter circuits 112, 116, 118, 120, 122 include TTL toECL translators to convert the TTL control signals to ECL signals. Inparticular, the converter circuit 112 includes a translator 113 havingan input terminal, D0, coupled to the TTL_TRIG_INHIB signal line and atranslator 114 having an input terminal, D1, coupled to the TTL_ARMsignal line. The Q0 output terminal of translator 113 is coupled to theTRIG_INHIB_PECL signal line and the Q0 output terminal of translator 114is coupled to the ARM_PECL signal line. Illustratively, the translators113, 114 are two portions of an ON Semiconductor type MC100ELT22 5V dualTTL to differential PECL translator. The converter circuit 116 includesa translator 117, illustratively an ON Semiconductor type MC100ELT20 5VTTL to differential PECL translator, having an input terminal, D,coupled to the TTL_TRIG_POLAR signal line and an output terminal, Q,coupled to the TRIG_POLARITY_PECL signal line.

Each of the converter circuits 118, 120, 122 includes a translator 119,121, 123, respectively, configured to convert a TTL control signal to anNECL signal. Illustratively the translators 119, 121, 123 are ONSemiconductor type MC100ELT24 5V TTL to differential ECL translators.The translator 119 includes an input terminal, D, coupled to theTLL_RST_TGL signal line and an output terminal, Q, coupled to theRST_TGL_NECL signal line. The translator 121 includes an input terminal,D, coupled to the TTL_HOLD_LATCH signal line and output terminals, Q and#Q, coupled to the RAMPLATCH_NECL and #RAMPLATCH_NECL signal lines,respectively. The translator 123 includes an input terminal, D, coupledto the TTL_OUT_INHIB signal line and output terminal, Q and #Q, coupledto the OUT_INHIB_NECL and #OUT_INHIB_NECL signal lines, respectively.Additional converter circuits may be used in other embodiments toconvert additional control signals to similar or other logic families asrequired by the particular embodiment or implementation of the circuit30.

Referring now particularly to FIGS. 10-12, the delay output circuit 42delays the initialization of the output delay event by the sum of thepulse width between the trigger event and a subsequent master clockpulse as represented by the stored digital value and the arbitraryinitialization delay time. Further, the circuit 42 produces an outputdelay event having a pulse width substantially equal to the arbitrarypulse width delay at an output port. In the illustrated embodiment, adigital-to-analog converter converts the stored digital value, orcalculated digital values based thereon, to a first and a second analogvoltage value. A first voltage ramp is initiated after the arbitraryinitialization delay time has elapsed as determined by the circuit 40.Once the first voltage ramp equals the first converted analog voltagevalue, a first output pulse is generated. A second voltage ramp isinitiated after the arbitrary pulse width delay time has elapse asdetermined by the circuit 40. Once the voltage of the second ramp equalsthe second converted analog voltage value, a second output pulse isgenerated. A delayed output event is subsequently produced having aninitialization edge (i.e., a rising edge) corresponding to the firstoutput pulse and a terminating edge (i.e., a falling edge) correspondingto the second output pulse.

Illustratively, the delay output circuit includes a digital-to-analogconverter 130, a first and second current-to-voltage converter 132, 134,respectively, a first and second translator 136, 138, respectively, afirst and second ramp generator 140, 142, respectively, a first andsecond comparator 144, 146, an AND gate 148, a JK flip-flop 150, and anintegrated driver 152. The DAC 130 illustratively is a Burr-Brown typeDAC2902 dual, 12 bit, 125 MSPS, digital-to-analog converter. Theconverters 132, 134 illustratively are Burr-Brown type OPA686/SOwideband, low noise, voltage feedback operational amplifiers. Thetranslators 136, 138 illustratively are ON Semiconductor type MC100ELT215V differential PECL to TTL translators. The ramp generators 140, 142illustratively are Burr-Brown type OPA660BB wide bandwidth operationaltransconductance and buffers. The comparators 144, 146 illustrativelyare Maxim type MAX9600 dual ECL ultra-high-speed comparators. The ANDgate 148 illustratively is an ON Semiconductor type MC100EL04 5V ECL2-input AND/NAND gate. The JK flip-flop 150 illustratively is an ONSemiconductor type MC100EL35 JK flip-flop and the integrated driver 152is an Analog Devices type AD53040 ultrahigh speed pin driver.

Referring particularly to FIG. 10, the DAC 130 includes a first andsecond input port having data input terminals D0_1-D11_1 and D0_2-D11_2,respectively. The D0_1-D11_1 and D0_2-D11_2 data terminals are wired ina parallel configuration to the data lines D0-D11, respectively (SeeFIG. 2). Data information is multiplexed on the data lines, D0-D11, bythe FPGA 100. The WRT1 and WRT2 control signals determine the particularport and associated data terminals of the DAC 130 to which the data onthe D0-D11 data lines is written. Accordingly, the WRT1 terminal of DAC130 is coupled to the WRT1 signal line and the WRT2 terminal of DAC 130is coupled to the WRT2 signal line. The DAC 130 converts the digitalvalues received at the first and second input ports to analog outputvalues produced at IOUT1 and IOUT2 terminals, respectively, of theDAC130. The outputs of the DAC 130 are current outputs and aresubsequently converted to voltage outputs by the converters 132, 134.The IOUT1 and #IOUT1 terminals of the DAC 130 are coupled to thenon-inverting input terminal (+) and inverting input terminal (−),respectively, of the converter 132. Similarly, the IOUT2 and #IOUT2terminals of the DAC 130 are coupled to the non-inverting input terminal(+) and the inverting input terminal (−), respectively, of the converter134. The output of converters 132, 134 are analog voltage values of thedigital values received on the data lines D0-DL1. In particular, theoutput of the converter 132 corresponds to the asynchronous timer 1voltage value which provides a target voltage level for the outputinitialization delay ramp and is coupled to the V_START_DELAY signalline. The output of the converter 132 corresponds to the asynchronoustimer 2 voltage value which provides a target voltage level for theoutput pulse width ramp and is coupled to the V_STOP_DELAY signal line.The operation of the voltage ramps is discussed in detail below inregard to FIG. 11.

Referring now particularly to FIG. 11, the V_START_DELAY andV_STOP_DELAY signal lines are coupled to the IN− terminals ofcomparators 144, 146, respectively. The TRIG_START_PECL and#TRIG_START_PECL signal lines are coupled to the Q and #Q inputs of thetranslator 136. The TRIG_STOP_PECL and #TRIG_STOP_PECL signal lines arecoupled to the Q and #Q inputs of translator 138. The translators 136,138 convert the PECL signals on the TRIG_START_PECL and TRIG_STOP_PECLsignal lines to TTL signals. The output of the translator 136 is coupledto the Vi input terminal of the operational transconductance amplifierof the ramp generator 140. The ramp generator 140 is configured as anintegrator and generates a voltage ramp when the generator 140 receivesthe TRIG_START_PECL signal. The OUTput terminal of ramp generator 140 iscoupled to the IN+ terminal of the comparator 144. The comparator 144produces a PECL low logic level pulse signal on the #Q output terminalwhen the ramp voltage of the ramp generator 140 is substantially equalto or greater than the analog voltage value of the V_START_DELAY datasignal. The output value of the comparator 144 is latched for anappropriate time period to produce an output pulse having a suitablepulse width using the RAMPLATCH_NECL and #RAMPLATCH_NECL signals. The #Qoutput terminal of the comparator 144 is coupled to the D0 inputterminal of the AND gate 148.

The output of translator 138 is coupled to the Vi input terminal of theoperational transconductance amplifier of the ramp generator 142. Theramp generator 142 is also configured as an integrator and generates avoltage ramp when the generator 142 receives the TRIG_STOP_PECL signal.The OUTput terminal of ramp generator 142 is coupled to the IN+ terminalof the comparator 146. The comparator 146 produces a PECL low logiclevel pulse signal on the #Q output terminal when the ramp voltage ofthe ramp generator 142 is substantially equal to or greater than theanalog voltage value of the V_STOP_DELAY data signal. Similar to thecomparator 144, the output value of the comparator 146 is latched for anappropriate time period to produce an output pulse having a suitablepulse width using the RAMPLATCH_NECL and #RAMPLATCH_NECL signals. The #Qoutput terminal of the comparator 146 is coupled to the D1 inputterminal of the AND gate 148.

The AND gate 148 produces a first PECL high logic level pulsecorresponding to the PECL low logic level pulse of the output ofcomparator 144 and a second PECL high logic level pulse corresponding tothe PECL low logic level pulse of the output of comparator 146 at its #Qoutput terminal. The #Q output terminal of the AND gate 148 is coupledto the CLK control terminal of the flip-flop 150. The flip-flop 150 iswired in a toggle configuration with a data value set to an NECL highlogic level. The reset terminal, R, of the flip-flop 150 is coupled tothe RST_TGL_NECL signal line thereby allowing the flip-flop 150 to bereset according to the RST_TGL_NECL signal. The output terminals, Q and#Q, of the flip-flop 150 are coupled to the PULSE_OUT_NECL and#PULSE_OUT_NECL signal lines. The flip-flop is toggled for a first timeat the rising edge of the first PECL high logic level pulse receivedfrom the AND gate 148 and toggled a second time at the rising edge ofthe second PECL high logic level pulse received form the AND gate 148.Accordingly, the PULSE_OUT_NECL signal is an NECL high logic level pulsewith a pulse width approximately equal to the width between the risingedges of the first and second PECL high logic level output pulses of theAND gate 148. It should be noted that the output signal of the flip-flop150 may or may not be synchronous with the master clock.

Referring now to FIG. 12, the PUSLE_OUT_NECL and #PULSE_OUT_NECL signallines are coupled to the DATA and #DATA terminals, respectively, of theintegrated driver 152. The integrated driver 152 translates the voltagelevel of the output delayed event signal from flip-flop 150 to a voltagelevel determined by the VO_HIGH and VO_LOW control signals. Theintegrated driver 152, therefore, permits the production of an outputdelayed event signal having a variety of logic voltage levels. Thecontrol signals, VO_HIGH and VO_LOW, may be preset voltage values orsupplied by other circuits. The OUT_INHIB_NECL control signal may beused to control the operation of the integrated driver 152. Accordingly,the OUT_INHIB_NECL and #OUT_INHIB_NECL control lines are coupled to theINH and #INH control terminals of the driver 152, respectively. TheV_OUT output terminal of integrated driver 152 is coupled to an outputport 154.

Referring now to FIGS. 15 and 16, the timing accuracy of circuits 10, 30is affected by the characteristics of the voltage ramp generated by theTime-to-Voltage Converter and Analog-to-Digital Converter circuits 18,38, respectively. The ramps generated by the internal circuitry of thecircuits 10, 30 may include timing uncertainties. For example, the startof the voltage ramps may include unknown internal delays, and therefore,may be asynchronous with the master clock. Similarly, the termination ofthe voltage ramps may be asynchronous with the master clock.Additionally, sub-circuits and individual components of circuits 10, 30,for example, the ADC 88 of circuit 38 (illustrated in FIG. 7), mayinclude unknown internal or propagation delays. Accordingly, aself-calibration method 230, illustrated in FIGS. 15 and 16, may be usedto compensate for the unknown timing uncertainties of the circuits 10,30. The self-calibration method 230 is discussed below in reference tothe circuit 30 which is one illustrative embodiment of the circuit 10with the understanding that the method 230 may be used with anyembodiment of the circuit 10.

The self-calibration method or process 230 begins with a process step232 in which portions of the circuit 30 are initialized. The initializedportions may include, for example, the master clock circuit 32 amongother sub-circuits of circuit 30. In process step 234, the process 230monitors for a leading edge of a clock cycle of a master clock pulsetrain. If no leading edge is detected, the process 230 loops back toprocess step 234 to continue monitoring for a leading edge of a masterclock cycle. An exemplary master clock pulse train 280 is illustrated inFIG. 16. In the illustrative embodiment, a leading edge of a masterclock cycle corresponds to a rising edge of the master clock cycle, butin other embodiments falling edges of master clock cycles may be used asleading edges of clock cycles.

Once process 230 detects a leading edge (i.e., a rising edge) of a clockcycle of the master clock pulse train 280, a first ramp 282 is initiatedin process step 236 at a time point 284 contemporaneously with thedetected leading edge of the master clock pulse train 280 as illustratedin FIG. 16. In the illustrative embodiment, the first ramp 282 isproduced by the ramp generator 86 of the TVC and ADC circuit 38 of thecircuit 30, but other ramp generation circuits may be used to calculateadditional inherent delays. It should be appreciated from FIG. 16 thatthe time point 284 may or may not be synchronous with the leading edgeof the clock cycle of the master clock pulse train 280 due to theinternal delays of the circuit 30.

The first ramp 282 continues for one full clock cycle of the masterclock pulse train 280. The process 230 monitors for the next leadingedge of the master clock pulse train 280 in process step 238. If noleading edge is detected, the process 230 loops back to process step 238to continue monitoring for the leading edge of the next master clockcycle. Once the next master clock cycle has been detected, the firstvoltage ramp 282 is stopped at a time point 286 contemporaneously withthe detected leading edge (i.e., the end of the previous master clockcycle) of the next master clock cycle in process step 240. Also inprocess step 240, the ramp voltage of the first ramp 282 is held for asuitable time period (e.g., a time period suitable to convert the analogvoltage value to a digital value). In the illustrative circuit 30, theramp voltage produced by the ramp generator 88 of the TVC and ADCcircuit 38 is held by controlling the quiescent current of the rampgenerator 88, but other methods of holding the ramp voltage may be usedsuch as a sample and hold circuit as discussed above in regard to FIG.6. Similar to time point 284, it should be appreciated that the timepoint 286 may be synchronous or asynchronous with the leading edge ofthe next master clock cycle due to the internal delays of the circuit30.

The analog voltage value of the first ramp 282 which is held in step 240is converted to a digital value in process step 242. In the illustrativecircuit 30, the analog ramp voltage value is converted to a digital rampvoltage value by the ADC 88 (see FIG. 7) of the TVC and ADC circuit 38.In process step 244, the digital ramp voltage value is stored in amemory location. Illustratively, the digital ramp voltage value isstored by the Memory Storage and Delay Calculation circuit 40 in aninternal memory location. Alternatively, the digital ramp voltage valuemay be stored in an external memory device.

The circuit 30 is reset in process step 246. In process step 248, theprocess 230 monitors for another leading edge of a clock cycle of themaster clock pulse train 280. If no leading edge is detected, theprocess 230 loops back to the process step 248 to continue monitoringfor another leading edge of a master clock cycle. Once process 230detects another leading edge (i.e., a rising edge) of a clock cycle ofthe master clock pulse train 280, a second ramp 292 is initiated inprocess step 250 at a time point 294 contemporaneously with the detectedleading edge of the master clock pulse train 280 as illustrated in FIG.16. Similar to the time point 284, the time point 294 may be synchronousor asynchronous with the leading edge of the clock cycle of the masterclock pulse train 280 due to the internal delays of the circuit 30.Additionally, in circuits 30 including more than one TVC and ADC circuit18, the circuits 18 may be used to initiate multiple ramps at a singletime point. In such an embodiment, the initiation time points 284, 294may or may not be synchronous with each. In those embodiments includinga single circuit 18, however, the second ramp 292 is initiated after thetermination of the first ramp 282 and, accordingly, the initiation timepoints 284, 294 are not synchronous with each other.

The second ramp 292 continues for two full clock cycles of the masterclock pulse train 280. The process 230 monitors for the second leadingedge of the master clock pulse train 280 in process step 252. If thesecond leading edge is not detected, the process 230 loops back toprocess step 252 to continue monitoring for the second leading edge ofthe master clock pulse train 280. Once the second leading edge of themaster clock pulse train 280 has been detected, the second voltage ramp292 is stopped at a time point 296 contemporaneously with the detectedsecond leading edge (i.e., the end of the previous two master clockcycles) of the master clock pulse train 280 in process step 254. Also inprocess step 254, the ramp voltage of the second ramp 282 is held for asuitable time period (e.g., a time period suitable to convert the analogvoltage value to a digital value). The time point 296 may be synchronousor asynchronous with the second leading edge of the master clock pulsetrain 280 due to the internal delays of the circuit 30.

The analog voltage value of the second ramp 282 which is held in step254 is converted to a digital value in process step 256. In process step258, the digital ramp voltage value is stored in a memory location suchas in the Memory Storage and Delay Calculation circuit 40. The circuit30 is subsequently reset in process step 260.

As a result of this self-calibration method 230, voltages at times 284,286, 294, and 296 are known. These four voltages and their respectivetimes are stored in memory, for example in the Memory Storage and DelayCalculation circuit 40, in process step 262. The process 230 calculatesthe slope and intercept of a voltage-to-time plot using the archiveddata values in process step 264. The voltage-to-time plot permitsreferencing voltage values to time values and time values to voltagevalues. The voltage-to-time plot may increase the circuit's accuracybecause the data points reflect some of the inherent delay times ofcircuit 30. The coefficients of the voltage-to-time plot aresubsequently stored in a memory location in process step 268 and theprocess 230 ends in process step 270.

Referring now to FIGS. 17 and 18, a system including two circuits 10 ofthe type illustrated in FIG. 1 may be used to measure the delay timebetween two input pulses utilizing a delay time measurement method orprocess 300. For example, a system having a first and a secondillustrative circuit 30 may be used with the method 300. Although themethod 300 is described below in reference to the circuit 30 which isone illustrative embodiment of the circuit 10, it should be appreciatedthat the method 300 is applicable to other embodiments of the circuit 10as well. Additionally, in some embodiments, a single master clockcircuit 12, 32 may be used in such systems.

The delay time measurement method 300 begins with a process step 302 inwhich the first and second circuits 30 are initialized. Initializationmay include, for example, initializing the master clock circuit 32. Anillustrative master clock pulse train 350 is shown in FIG. 18. Inprocess step 304, the trigger circuits of the first and second circuits30 are armed and prepared for the detection of trigger events. Forexample, the window voltages are determined and supplied to the SignalConditioning and Edge Detection Circuits 34 of the first and secondcircuits 30 and the flip-flops of the Resynchronization and Jitter Pulseconstruction circuits 36 of the first and second circuits 30 are presetand armed.

In process step 306, the process 300 determines if a first trigger event352 has been received by the first circuit 30. If the first circuit 30received the first trigger event 352, the process 300 advances toprocess step 310 which will be described below. If the first circuit 30did not receive the first trigger event 352, the process 300 determinesif a second trigger event 354 has been received by the second circuit 30in process step 208. If the second circuit 30 received the secondtrigger event 354, the process 300 advances to process step 322 whichwill be described below. If the second circuit 30 has not received thesecond trigger event 354, the process 300 loops back to process step 306to determine if the first circuit 30 has received the first triggerevent 352. Accordingly, the process 300 continues to monitor for one ofthe trigger events 352, 354 by advancing through the monitoring loopformed from the process steps 306 and 308.

Referring back to process step 306, if the first circuit 30 received thefirst trigger event 352 in process step 306, the phase error between thefirst trigger event 352 and the master clock pulse train 350 isdetermined in process step 310. Illustratively, the phase error isdetermined by initiating a first voltage ramp 356 contemporaneously withthe detection of the first trigger event 352 at a time point 358. Thefirst ramp 356 continues until a convenient leading edge of the masterclock pulse train 350. Illustratively, the first ramp 356 continues fora time period equal to the phase error between the first trigger event352 and the leading edge of the next cycle of the master clock pulsetrain 350 plus one additional clock cycle, i.e., a time point 360 at therising edge of the second master clock cycle after the detection of thefirst trigger event 352. The time point 358 may or may not besynchronous with the detected first trigger event 352 due to inherentdelays within the circuits 30. Similarly, the time point 360 may or maynot be synchronous with the leading edge of the clock cycle of themaster clock pulse train 350 due to inherent delays within circuits 30.However, the self-calibration method 230 may be used to compensate forthe inherent delays of the circuits 30 as discussed above in regard toFIGS. 15 and 16.

After the first ramp 356 has stopped rising at the time point 360, thevoltage value of the ramp 356 is digitized and the digital value isstored in a memory location. Illustratively, the voltage value of theramp 356 is digitized by the ADC 88 (see FIG. 7) of the TVC and ADCcircuit 38 and stored in the Memory Storage and Delay Calculationcircuit 40 (see FIG. 8). In process step 312, a synchronous counter,illustrated in FIG. 18 by synchronous counter 368, is initiated to countthe number of elapsed master clock cycles. Illustratively, thesynchronous counter 368 is initiated at the rising edge of the secondmaster clock cycle after the first trigger event 352 andcontemporaneously with the time point 362. In process step 314, theprocess 300 monitors for the second trigger event 354. If the secondcircuit 30 has not received the second trigger event 354, the process300 loops back to process step 314 to continue monitoring for the secondtrigger event 354. If the second circuit 30 has received the secondtrigger event 354, the phase error between the second trigger event 354and the master clock pulse train 350 is determined in process step 316.Illustratively, the phase error is determined by initiating a secondvoltage ramp 362 contemporaneously with the detection of the secondtrigger event 354 at a time point 364. The second ramp 362 continuesuntil a convenient leading edge of the master clock pulse train 350.Illustratively, similar to the first ramp 356, the second ramp 362continues for a time period equal to the phase error between the secondtrigger event 354 and the leading edge of the next cycle of the masterclock pulse train 350 plus one additional clock cycle, i.e., a timepoint 366 at the rising edge of the second master clock cycle after thedetection of the second trigger event 354. The time point 364 may or maynot be synchronous with the detected second trigger event 354 due toinherent delays within the circuits 30. Similarly, the time point 366may or may not be synchronous with the leading edge of the clock cycleof the master clock pulse train 350 due to inherent delays withincircuits 30. Again, the self-calibration method 230 may be used tocompensate for the inherent delays of the circuits 30 as discussed abovein regard to FIGS. 15 and 16.

After the second ramp 362 has stopped rising at the time point 366, thevoltage value of the ramp 362 is digitized and the digital value isstored in a memory location. Illustratively, the voltage value of theramp 362 is digitized by the ADC 88 (see FIG. 7) of the TVC and ADCcircuit 38 and stored in the Memory Storage and Delay Calculationcircuit 40 (see FIG. 8). In process step 318, the synchronous counter isterminated and the value of the synchronous counter is stored in amemory location: Illustratively, the synchronous counter is terminatedcontemporaneously with the time point 366 at the rising edge of thesecond master clock cycle after the second trigger event 354. The timevalue of the synchronous counter is stored in the Memory Storage andDelay Calculation circuit 40. The process 300 subsequently advances toprocess step 320 which will be described below.

Referring back to process step 308, if the second circuit 30 receivedthe second trigger event 354 in process step 308, the process 300performs a process routine formed of process steps 322-330 which issimilar to the respective process steps of 310-318. The process routineof process steps 322-330 and process steps 310-318 differ in that thesecond voltage ramp 362 is initiated prior to the first voltage ramp 356because the second trigger event 354 is received prior to the firsttrigger event 352. Additionally, in the process routine of process steps322-330, the synchronous counter is initiated at the termination of thesecond ramp 362 and is halted at the termination of the first ramp 356.However, the calculation process of the phase error of the triggerevents 352, 354 is similar in both process routines. Accordingly, theprocess 300 operates in substantially the same manner independent ofwhether the first trigger event 352 occurs before or after the secondtrigger event 354.

In process step 320, after both triggering events 352, 354 have beenreceived in any order either through the process routine of processsteps 310-318 or the process routine of process steps 322-330, the delaytime between the two triggering events 352, 354 is calculated by theprocess 300. Illustratively, the delay time between the two triggerevents 352, 354 is calculated by summing the value of the synchronouscounter with the time value of the voltage ramp associated with thefirst received trigger event (i.e. the first voltage ramp 356 if thefirst trigger event 352 is received prior to the second trigger event354 and the second voltage ramp 362 if the second trigger event 354 isreceived prior to the first trigger event 352). The time value of thevoltage ramp associated with the second received trigger event (i.e. thesecond voltage ramp 362 if the first trigger event 352 is received priorto the second trigger event 354 and the first voltage ramp 356 if thesecond trigger event 354 is received prior to the first trigger event352) is then subtracted from this sum. The resulting value, therefore,is the delay time between the first received trigger event and thesecond received trigger event. The time value of the digitized voltageramp values may be determined by using the calibration coefficientsdetermined by the self-calibration method 230 described above in regardto FIGS. 15 and 16. The process 300 subsequently terminates in processstep 332.

It should be appreciated that the delay time calculation process ofprocess step 320 may be configured or otherwise altered to accommodateother timing factors including, but not limited to, fixed and knowndelays. Knowledge of the time delay between two trigger pulses may havemany applications including, for example, measuring the propagationdelay in electrical circuitry, RADAR, control circuits, and distancemeasurement circuitry.

There are many advantages of the concepts of the present disclosurearising from the various features of the apparatus and methods describedherein. Other embodiments of the apparatus and methods of the presentdisclosure may not include all of the features described yet stillbenefit from at least some of the advantages of such features. Those ofordinary skill in the art may readily devise their own implementationsof the apparatus and methods of the present disclosure that incorporateone or more of the features of the present disclosure and fall withinthe spirit and scope of the invention defined by the appended claims.

1. A method for measuring a time between two trigger events, the methodcomprising initiating a first ramp voltage for the duration of a timebetween a first trigger event and a subsequent clock pulse; initiating atime counter contemporaneously with the end of the first ramp voltage;initiating a second ramp voltage for the duration of a time between asecond trigger event and a subsequent clock pulse; terminating the timecounter contemporaneously with the end of the second ramp voltage; andcalculating the delay between the first trigger event and the secondtrigger event.
 2. The method of claim 52, further comprising convertinga peak voltage of the first ramp voltage to a first time value andconverting a peak voltage of the second ramp voltage to a second timevalue.
 3. The method of claim 52, wherein calculating the delay betweenthe first trigger event and the second trigger event comprisesconverting a peak voltage of the first ramp voltage to a first timevalue, converting a peak voltage of the second ramp voltage to a secondtime value, summing the first time value with the time counter, andsubtracting the second time value from the time counter.
 4. A method forself-calibrating a delay measurement and generation circuit, the methodcomprising: initiating a first voltage ramp for about one clock cycle;storing a first peak voltage of the first voltage ramp; initiating asecond voltage ramp for about two clock cycles; storing a second peakvoltage of the second voltage ramp; calculating the slope and interceptof a voltage-to-time line including the first and second peak voltages.5. The method of claim 55, wherein storing a first peak voltage of thefirst voltage ramp comprises sampling and holding the voltage ramp afterabout one clock cycle.
 6. The method of claim 55, wherein storing asecond peak voltage of the second voltage ramp comprises sampling andholding the voltage ramp after about one clock cycle.
 7. The method ofclaim 55, wherein storing a first peak voltage of the first voltage rampcomprises converting the first peak voltage to a first digital value andsubsequently storing the first digital value in a memory location. 8.The method of claim 55, wherein storing a second peak voltage of thesecond voltage ramp comprises converting the second peak voltage to asecond digital value and subsequently storing the second digital valuein a memory location.
 9. The method of claim 55, further comprisingstoring the slope and intercept of the voltage-to-time line in a memorylocation.